Tracking the Progress of the CHIPS R&D Initiatives

Last updated December 10, 2024

The CHIPS Act represents the most significant federal investment ever made in the U.S. semiconductor industry, including a substantial $13 billion investment over 5 years in chip research and development (R&D) programs between the Department of Commerce ($11 billion) and the Department of Defense ($2 billion). The Programs include:

SIA will track the progress of each program below, and more information is available at CHIPS.gov.

CHIPS R&D funds will be allocated over multiple years and will be used to sustain various initiatives and programs, operate facilities, support funding opportunities, conduct research projects, promote workforce development, and more.

CHIPS National Semiconductor Technology Center (NSTC)

The NSTC is a public-private consortium funded by the CHIPS for America Program. Members of the NSTC will have access to facilities, partners, an investment fund, and additional resources and funding opportunities for semiconductor R&D and workforce development. The NSTC will be operated by the National Center for the Advancement of Semiconductor Technology (Natcast). The NSTC was established to “conduct research and prototyping of advanced semiconductor technology and grow the domestic semiconductor workforce to strengthen the economic competitiveness and security of the domestic supply chain” (15 USC § 4656(c)(1)).

Background

The CHIPS NSTC Program Office, led by Director Dr. Jay Lewis, is leading the creation of key elements of the NSTC. The NSTC is funded by CHIPS for America and operated by Natcast, which is led by CEO Deirdre Hanford.

NSTC Facilities
- EUV Accelerator – Albany, NY
- Collaboration & Design Facility – Sunnyvale, CA
- NSTC Prototyping and NAPMP Piloting Facility – TBD
NSTC Strategic Plan
NSTC Membership
Release of 2024 roadmap

SIA’s Recommendations Promoting the Success of the NSTC – Report and Blog Post

Learn more at CHIPS.gov.

Funding Opportunities

Jumpstart R&D Programs

Artificial Intelligence Driven RF Integrated Circuit Design Enablement (AIDRFIC) - $30 million - Awardees:
- University of Texas - Austin
- Keysight Technologies
- Princeton University
Test Vehicle innovation pipeline (TVIP) - $55 million
PFAS Reduction and Innovation in Semiconductor Manufacturing (PRISM) - $35 million

Workforce Center of Excellence

NSTC Workforce Partner Alliance (WFPA) Program - $11 million - Awardees:
- Maricopa County Community College District (MCCCD)
- University of California, Los Angeles (UCLA)
- Idaho Technology Council (ITC)
- University of Illinois Urbana-Champaign (UIUC)
- American Federation of Teachers EducationAL Foundation (AFTEF)
- Rochester Institute of Technology (RIT)
- Texas A&M University

CHIPS National Advanced Packaging Manufacturing Program (NAPMP)

The NAPMP program was established “to strengthen semiconductor advanced test, assembly, and packaging capability in the domestic semiconductor ecosystem” (15 USC §4656(d)).

Background

The NAPMP is led by Director Dr. Dev Palmer and is seeking to invest in the below R&D areas, alongside an advanced packaging piloting facility to be co-located with the NSTC prototyping facility

Learn more at CHIPS.gov.

Funding Opportunities

NOFO #1 - Materials & Substrates - $150 million - Awardees
- Arizona State University
- Applied Materials
- Absolics
NOFO #2 - Remaining 5 R&D areas - $1.6 billion
- Equipment, Tools, Processes, and Process Integration - $450 million
- Power Delivery and Thermal Management - $250 million
- Connector Technology, Including Photonics and Radio Frequency (RF) - $250 million
- Chiplets Ecosystem - $300 million
- Co-design/Electronic Design Automation (EDA) - $250 million

CHIPS Metrology Program

The CHIPS Metrology Program is a NIST R&D program “to enable advances and breakthroughs in measurement science, standards, material characterization, instrumentation, testing, and manufacturing capabilities that will accelerate the underlying research and development for metrology of next generation microelectronics and ensure the competitiveness and leadership of the United States within this sector” (15 USC §4656(e)).

The Latest

Director Dr. Marla Dowell leads the CHIPS Metrology Program, which has various ongoing research activities and is leading NIST semiconductor and microelectronics metrology efforts centered around 7 grand challenges. The Program also features a Metrology Community of Practice.

CHIPS Metrology Grand Challenges – Metrology Gaps in the Semiconductor Ecosystem

Metrology for Materials Purity, Properties, and Provenance
Advanced Metrology for Future Microelectronics Manufacturing
Enabling Metrology for Integrating Components in Advanced Packaging
Modeling and Simulating Semiconductor Materials, Designs, and Components
Modeling and Simulating Semiconductor Manufacturing Processes
Standardizing New Materials, Processes, and Equipment for Microelectronics
Metrology to Enhance Security and Provenance of Microelectronic-based Components and Products

Learn more at CHIPS.gov.

Funding Opportunities

Ongoing Projects and Programs
Small Business Innovation Research (SBIR) - $54 million (Phase 1 - $4.8 million) - Awardees
- Sigray Inc. – Concord, CA
- Photon Spot, Inc. – Monrovia, CA
- HighRI Optics, Inc – Oakland, CA
- Direct Electron LP – Rancho Bernardo, CA
- ReconRF – San Diego, CA
- Photothermal Spectroscopy Corporation – Santa Barbara, CA
- PrimeNano Inc. – Santa Clara, CA
- Tech-X Corporation – Boulder, CO
- Vapor Cell Technologies – Boulder, CO
- Octave Photonics – Louisville, CO
- Virtual EM, Inc – Ann Arbor, MI
- The Provenance Chain Network – Portland, OR
- Tiptek LLC – West Chester, PA
- Exigent Solutions – Frisco, TX
- Laser Thermal Analysis, Inc. – Charlottesville, VA
- Hummingbird Scientific – Olympia, WA
- Steam Instruments, Inc. – Madison, WI

CHIPS Manufacturing USA Institute

The CHIPS Manufacturing USA institute will be “an entirely new and unique institute that facilitates the manufacturing of semiconductor digital twins” to “reduce U.S. chip development and manufacturing costs, such as by improving capacity planning, production optimization, facility upgrades, and real-time process adjustments” (CHIPS.gov).

The Latest

Led by Director Dr. Eric Forsythe, CRDO launched a NOFO for up to $285 million the establishment of a Manufacturing USA Institute focused on digital twins for the semiconductor industry. Digital twins are virtual models that mimic the structure, context, and behavior of a physical counterpart.

Learn more at CHIPS.gov.

CHIPS Digital Twins Manufacturing USA Institute

The objectives of the Institute include:

Convene stakeholders across the semiconductor production ecosystem
Improve the state of the art in manufacturing-relevant digital twins
Significantly reduce cost for U.S. chip development and manufacturing
Improve development cycle times of semiconductor product innovation
Advance digital twin-enabled curricula for training a domestic semiconductor workforce
Create a digital twin marketplace for industry to access digital models

DOD Microelectronics Commons (ME Commons)

ME Commons public-private partnership operated to incentivize the formation of one or more consortia of companies to ensure the development and production of measurably secure microelectronics, including integrated circuits, logic devices, memory, and the packaging and testing practices that support these microelectronic components by the Department of Defense, the intelligence community, critical infrastructure sectors, and other national security applications.

The Latest

The ME Commons awarded $269 million to 33 projects in 27 states. Additional information about the projects is forthcoming, with preliminary detail below

Quantum: 4 projects, $32 million
Secure edge computing: 4 projects, $25 million
5G/6G: 5 projects, $42 million
Electromagnetic warfare: 6 projects, $51 million
Commercial leap-ahead: 7 projects, $38 million
Artificial intelligence, 7 projects, $42 million
Cross-Hub Enablement Solution (CHES) award: $39 million.

The goal of the Microelectronics Commons programs is to address the "valley of death" and facilitate the lab-to-fab transition for microelectronics research with defense applications. The ME Commons is led by Dr. Dev Shenoy at DOD and Stephanie Lin at NSTXL.

"Unique Commons Hub Initiatives Nurture Workforce Development" - July 1 Blog post
Call for Topics released on June 24, 2024 - Topics due July 24, 2024. Topic submissions will only be accepted from the eight Microelectronics Commons Hubs.
- CFT Technical Guidance
ME Commons Request for Projects November 2023 - webinar and resources
ME Commons Annual Meeting October 2023 - resources
The Department of Defense selected 8 hubs to lead its ME Commons programs in Sept. 2023 (right)
Overview Presentation October 2022 - slides

CHIPS R&D Programs

Tracking the Progress of the CHIPS R&D Initiatives

Last updated December 10, 2024

CHIPS National Semiconductor Technology Center (NSTC)

Background

SIA’s Recommendations Promoting the Success of the NSTC – Report and Blog Post

Learn more at CHIPS.gov.

Funding Opportunities

CHIPS National Advanced Packaging Manufacturing Program (NAPMP)

The NAPMP program was established “to strengthen semiconductor advanced test, assembly, and packaging capability in the domestic semiconductor ecosystem” (15 USC §4656(d)).

Background

Learn more at CHIPS.gov.

Funding Opportunities

CHIPS Metrology Program

The Latest

Learn more at CHIPS.gov.

Funding Opportunities

CHIPS Manufacturing USA Institute

The Latest

Learn more at CHIPS.gov.

CHIPS Digital Twins Manufacturing USA Institute

DOD Microelectronics Commons (ME Commons)

The Latest

Learn more at MicroelectronicsCommons.org and CTO.mil.